? semiconductor components industries, llc, 2001 october, 2001 rev. 7 1 publication order number: sn74ls195a/d sn74ls195a universal 4-bit shift register the sn74ls195a is a high speed 4-bit shift register offering typical shift frequencies of 39 mhz. it is useful for a wide variety of register and counting applications. it utilizes the schottky diode clamped process to achieve high speeds and is fully compatible with all on semiconductor ttl products. ? typical shift right frequency of 39 mhz ? asynchronous master reset ? j, k inputs to first stage ? fully synchronous serial or parallel data transfers ? input clamp diodes limit high speed termination effects guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 4.75 5.0 5.25 v t a operating ambient temperature range 0 25 70 c i oh output current high 0.4 ma i ol output current low 8.0 ma low power schottky soic d suffix case 751b plastic n suffix case 648 16 1 16 1 device package shipping ordering information sn74ls195an 16 pin dip 2000 units/box sn74ls195ad soic16 38 units/rail sn74ls195adr2 soic16 2500/tape & reel http://onsemi.com
sn74ls195a http://onsemi.com 2 connection diagram dip (top view) parallel enable (active low) input parallel data inputs first stage j (active high) input first stage k (active low) input clock (active high going edge) input master reset (active low) input parallel outputs complementary last stage output pe p 0 - p 3 j k cp mr q 0 - q 3 q 3 0.5 u.l. 0.5 u.l. 0.5 u.l. 0.5 u.l. 0.5 u.l. 0.5 u.l. 10 u.l. 10 u.l. 0.25 u.l. 0.25 u.l. 0.25 u.l. 0.25 u.l. 0.25 u.l. 0.25 u.l. 5 u.l. 5 u.l. notes: a) 1 ttl unit load (u.l.) = 40 a high/1.6 ma low. high low (note a) loading pin names logic symbol 2 10 3 456 7 11 12 13 14 15 1 9 j pe cp k mr p 0 p 1 p 2 p 3 q 0 q 1 q 2 q 3 q 3 v cc = pin 16 gnd = pin 8 note: the flatpak version has the same pinouts (connection diagram) as the dual inline package. 14 13 12 11 10 9 123456 7 16 15 8 v cc mr q 0 q 1 q 2 q 3 cp q 3 pe jk p 0 p 1 p 2 p 3 gnd
sn74ls195a http://onsemi.com 3 logic diagram jp 0 p 1 p 2 p 3 cp pe k mr q 0 q 0 q 1 q 3 r cp s c d q 0 q 2 q 3 14 1 267 3 4 5 9 11 12 10 13 15 v cc = pin 16 gnd = pin 8 = pin numbers r cp s c d q 0 r cp s c d q 2 q 3 r cp s c d q 3 functional description the logic diagram and truth table indicate the functional characteristics of the ls195a 4-bit shift register. the device is useful in a wide variety of shifting, counting and storage applications. it performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. the ls195a has two primary modes of operation, shift right (q 0 q 1 ) and parallel load which are controlled by the state of the parallel enable (pe ) input. when the pe input is high, serial data enters the first flip-flop q 0 via the j and k inputs and is shifted one bit in the direction q 0 q 1 q 2 q 3 following each low to high clock transition. the jk inputs provide the flexibility of the jk type input for special applications, and the simple d type input for general applications by tying the two pins together. when the pe input is low, the ls195a appears as four common clocked d flip-flops. the data on the parallel inputs p 0 , p 1 , p 2 , p 3 is transferred to the respective q 0 , q 1 , q 2 , q 3 outputs following the low to high clock transition. shift left operations (q 3 q 2 ) can be achieved by tying the q n outputs to the p n1 inputs and holding the pe input low. all serial and parallel data transfers are synchronous, occurring after each low to high clock transition. since the ls195a utilizes edge-triggering, there is no restriction on the activity of the j, k , p n and pe inputs for logic operation e except for the set-up and release time requirements. a low on the asynchronous master reset (mr ) input sets all q outputs low, independent of any other input condition. mode select e truth table operating modes inputs outputs operating modes mr pe j k p n q 0 q 1 q 2 q 3 q 3 asynchronous reset l x x x x l l l l h shift, set first stage h h h h x h q 0 q 1 q 2 q 2 shift, reset first h h i i x l q 0 q 1 q 2 q 2 shift, toggle first stage h h h i x q 0 q 0 q 1 q 2 q 2 shift, retain first stage h h i h x q 0 q 0 q 1 q 2 q 2 parallel load h i x x p n p 0 p 1 p 2 p 3 p 3 l = low voltage levels h = high voltage levels x = don't care i = low voltage level one set-up time prior to the low to high clock transition. h = high voltage level one set-up time prior to the low to high clock transition. p n (q n ) = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the low to high clock transition.
sn74ls195a http://onsemi.com 4 dc characteristics over operating temperature range (unless otherwise specified) limits symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 0.8 v guaranteed input low voltage for all inputs v ik input clamp diode voltage 0.65 1.5 v v cc = min, i in = 18 ma v oh output high voltage 2.7 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table v ol out p ut low voltage 0.25 0.4 v i ol = 4.0 ma v cc = v cc min, v in v il or v ih v ol output low voltage 0.35 0.5 v i ol = 8.0 ma v in = v il or v ih per truth table i ih in p ut high current 20 m a v cc = max, v in = 2.7 v i ih input high current 0.1 ma v cc = max, v in = 7.0 v i il input low current 0.4 ma v cc = max, v in = 0.4 v i os short circuit current (note 1) 20 100 ma v cc = max i cc power supply current 21 ma v cc = max note 1: not more than one output should be shorted at a time, nor for more than 1 second. ac characteristics (t a = 25 c) limits symbol parameter min typ max unit test conditions f max maximum clock frequency 30 39 mhz t plh t phl propagation delay, clock to output 14 17 22 26 ns v cc = 5.0 v c l = 15 p f t phl propagation delay, mr to output 19 30 ns c l = 15 pf ac setup requirements (t a = 25 c) limits symbol parameter min typ max unit test conditions t w cp clock pulse width 16 ns t w mr pulse width 12 ns t s pe setup time 25 ns t s data setup time 15 ns v cc = 5.0 v t rec recovery time 25 ns cc t rel pe release time 10 ns t h data hold time 0 ns
sn74ls195a http://onsemi.com 5 definitions of terms setup time(t s ) eis defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from low to high in order to be recognized and transferred to the outputs. hold time (t h ) e is defined as the minimum time following the clock transition from low to high that the logic level must be maintained at the input in order to ensure continued recognition. a negative hold time indicates that the correct logic level may be released prior to the clock transition from low to high and still be recognized. recovery time (t rec ) e is defined as the minimum time required between the end of the reset pulse and the clock transition from low to high in order to recognize and transfer high data to the q outputs. ac waveforms the shaded areas indicate when the input is permitted to change for predictable output performance. figure 1. clock to output delays and clock pulse width figure 2. master reset pulse width, master reset to output delay and master reset to clock recovery time conditions: mr = h *q 0 state will be determined by j and k inputs. 1.3 v 1.3 v 1.3 v 1.3 v clock output pe q n = p n q n * = q n-1 t rel t rel t s (l) t s (h) load parallel data load serial data shift right 1.3 v conditions: pe = l po = p 1 = p 2 = p 3 = h conditions: mr = h *j and k set-up time affects q 0 only pe j & k p 0 p 1 p 2 p 3 clock output* clock clock output output t s (h) t h (l) = 0 t h (h) = 0 t h (h) = 0 t s (h) t h (l) = 0 t s (l) t phl t plh t s (l) mr t rec t phl 1.3v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v t w conditions: j = pe = mr = h k = l t w 1.3 v figure 3. setup (t s ) and hold (t h ) time for serial data (j & k ) and parallel data (p 0 , p 1 , p 2 , p 3 ) figure 4. setup (t s ) and hold (t h ) time for pe input
sn74ls195a http://onsemi.com 6 package dimensions n suffix plastic package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
sn74ls195a http://onsemi.com 7 d suffix plastic soic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
sn74ls195a http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. sn74ls195a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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